Please refer to FIG. 1, which is a diagram illustrating a frequency synthesizer according to the prior art. The frequency synthesizer is a kind of component used for providing various kinds of frequencies in one or many reference frequency circuits. Usually, in the frequency synthesizer, the multiply phase locked loop would be adopted therein in order to obtain a series of frequency signals. Take it as the example the frequency synthesizer architecture 1 illustrating in FIG. 1, where a phase locked loop 80 receives a reference frequency 81; a UP and DN signal are outputted by a phase frequency detector 91 in the phase locked loop 80; a digital comparison signal is transformed into an analogy current signal by a charge pump 92; a control voltage Vctrl is then obtained by filtering the analogy current signal through a loop filter 93 (low-pass filter); and this control voltage Vctrl is used for controlling a signal output of a voltage controlled oscillator (VCO) 94 and the signal output then passes a specific frequency divider. Finally, in accordance with the aforementioned, signals from different frequency bands could be generated via a single sideband mixer 82.
Please keep referring to FIG. 1. For the present state of the art, the phase locked loop 80 illustrated in FIG. 1 includes a loop filter 93, a frequency divider 95/96 and a voltage control oscillator 94, wherein the loop filter 93 is a low-pass filter that is usually consisted of the resistances and the capacitors etc. so that it would occupy more area for the circuit.
The frequency divider could be categorized into two types, one is an injected locked frequency divider (ILFD) and the other is a digital frequency divider. The former type has a lower power consuming when a higher operation frequency is adopted thereby, and it could be used to define a more precise phase relationship. Please keep referring to FIG. 1. Since the orthogonal signals 83/84 of a I-channel and a Q channel are required to be involved in the mixer 82 of the multiply bands system so as to synthesize the signal 85 of a specific wave band and the phase deviation will determine whether the other frequency signals could be suppressed in order to provide a smaller spur wave on the outputted frequency band, a precise phase could helpfully enhance the performance of the in-band spur wave; and the latter type has a lower workable frequency, could provide a fractional frequency divider ratio, has no static power consuming and could further reduce the dynamic power consuming through the True-Signal-Phase-Clock (TSPC) technique, but the phase relationship could not be guaranteed. Therefore, in this conventional way, the ILFD would be chosen to be used following the VCO, for instance a first frequency divider 95, but the digital frequency divider would be chosen to be used in front of the phase detector, for instance a second frequency divider.
The VCO 94 could be a coupled looped VCO 200 (referring to FIG. 2(a)) and since it has a lesser order, it saves energy and could perform better in the aspect of the noise than the conventional looped VCO 942 (referring to FIG. 3). However, due to the improvement of the technology, the scale of the circuit becomes more and more miniature and the magnitude of the power source are also decreased so that the permitted oscillating amplitude is also decreased thereaccording. In order to deal with the variation of the manufacturing process, for the VCO, a smaller range of the control voltage is required and simultaneously the required bandwidth must also be covered thereby. (referring to FIG. 2(b)) for a conventional single order VCO circuit 943, a fixed resistive load 944 is used to adjust the characteristic curve of the VCO voltage with respect to the frequency so as to raise the Kvco (the variation of the frequency/the control voltage to the linear portion of the curve and magnitude of the slope to the linear portion of the curve). But the raise of the Kvco would influence the performance to the spur wave. Besides, it frequently needs to generate a series of frequencies with fractional ratio in the orthogonal frequency division multiply super wideband, but the first frequency divider 95 of the injected locked type could merely generate an integer ratio. Hence, a fractional type circuit shall be therefore provided, for instance the multiplication circuit 86. In prior art, the fractional type circuit is usually consisted of a multiplier and a divider. In terms of the multiplication circuit 86, it is consisted of a multiplier 87 that is combined with a divider 88. For example, in the conventional technique, a divided-by-2 circuit 98 (referring to FIGS. 5(a), 5(b)) is merged with a multiply-by-3 circuit 97 (referring to FIG. 4) in order to complete the purpose to multiply by 1.5. Nevertheless, since these two circuits are usually operated with a higher workable frequency that consumes massive power and the multiply-by-3 circuit includes the passive component, these two circuits occupy more circuit area.
To overcome the mentioned drawbacks of the prior art, a surface treatment method and device thereof are provided.